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plx9080.h

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00001 /* -*-C-*- 00002 ******************************************************************************* 00003 * 00004 * File: plx9080.h 00005 * Description: PLX 9080 registers 00006 * 00007 ******************************************************************************* 00008 */ 00009 /* 00010 * Copyright 2001 Free Software Foundation, Inc. 00011 * 00012 * This file is part of GNU Radio 00013 * 00014 * GNU Radio is free software; you can redistribute it and/or modify 00015 * it under the terms of the GNU General Public License as published by 00016 * the Free Software Foundation; either version 2, or (at your option) 00017 * any later version. 00018 * 00019 * GNU Radio is distributed in the hope that it will be useful, 00020 * but WITHOUT ANY WARRANTY; without even the implied warranty of 00021 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00022 * GNU General Public License for more details. 00023 * 00024 * You should have received a copy of the GNU General Public License 00025 * along with GNU Radio; see the file COPYING. If not, write to 00026 * the Free Software Foundation, Inc., 59 Temple Place - Suite 330, 00027 * Boston, MA 02111-1307, USA. 00028 */ 00029 00030 /* 00031 * References: 00032 * 00033 * PLX 9080 PCI Data Book version 1.06 00034 * http://www.plxtech.com/download/9080/databook/9080db-106.pdf 00035 */ 00036 00037 /* 00038 * There are *lots* of registers in the PLX 9080. I'm only defining the 00039 * one's I'm using... 00040 */ 00041 00042 #ifndef _PLX9080_H_ 00043 #define _PLX9080_H_ 00044 00045 /* 00046 * pci configuration registers are standard. 00047 * see linux/pci.h 00048 */ 00049 00050 /* 00051 * Local configuration registers. 00052 * Offsets are relative to PCI side, add PLX_LCL_OFFSET for local address 00053 */ 00054 00055 #define PLX_LCL_OFFSET 0x80 // offset of regs from local side 00056 00057 00058 #define PLX_LAS0RR 0x00 // Local Address Space 0 Range Register PCI-to-local 00059 #define PLX_LAS0BA 0x04 // Local Address Space 0 Local Base Address (Remap) Register 00060 #define PLX_MARBR 0x08 // Mode/Arbitration Register 00061 #define PLX_BIGEND 0x0c // Big/Little Endian Register 00062 #define PLX_EROMRR 0x10 // Expansion ROM Range Register 00063 #define PLX_EROMBA 0x14 // Expansion ROM Local Base Address (Remap) Register 00064 #define PLX_LBRD0 0x18 // Local Address Space 0 / Expn ROM Bus Region Desc 00065 #define PLX_DMRR 0x1c // Local Range Register for Direct Master to PCI 00066 #define PLX_DMLBAM 0x20 // Local Bus Base Addr Reg for Direct Master to PCI Memory 00067 #define PLX_DMLBAI 0x24 // Local Base Addr Reg for Direct Master to PCI IO/CFG 00068 #define PLX_DMPBAM 0x28 // PCI Base Addr (Remap) Reg for Direct Master to PCI Memory 00069 #define PLX_DMCFGA 0x2c // PCI Config Addr Reg for Direct Master to PCI IO/CFG 00070 00071 #define PLX_LAS1RR 0xf0 // Local Addr Space 1 Range Reg for PCI-to-Local Bus 00072 #define PLX_LAS1BA 0xf4 // Local Addr Space 1 Local Base Addr (Remap) Register 00073 #define PLX_LBRD1 0xf8 // Local Addr Space 1 Bus Region Desc Reg 00074 00075 /* 00076 * Runtime registers. 00077 * Offsets are relative to PCI side. 00078 */ 00079 00080 #define PLX_MBOX0 0x40 00081 #define PLX_MBOX1 0x44 00082 #define PLX_MBOX2 0x48 00083 #define PLX_MBOX3 0x4c 00084 #define PLX_MBOX4 0x50 00085 #define PLX_MBOX5 0x54 00086 #define PLX_MBOX6 0x58 00087 #define PLX_MBOX7 0x5c 00088 00089 #define PLX_P2LDBELL 0x60 // PCI-to-Local Doorbell Reg 00090 #define PLX_L2PDBELL 0x64 // Local-to-PCI Doorbell Reg 00091 00092 #define PLX_INTCSR 0x68 // Interrupt Control/Status 00093 00094 # define PLX_LSERR_ENABLE 0x00000001 00095 # define PLX_LSERR_PE 0x00000002 00096 # define PLX_SERR 0x00000004 00097 # define PLX_MBOX_IE 0x00000008 00098 # undef PLX_UNUSED /* 0x00000010 */ 00099 # undef PLX_UNUSED /* 0x00000020 */ 00100 # undef PLX_UNUSED /* 0x00000040 */ 00101 # undef PLX_UNUSED /* 0x00000080 */ 00102 # define PLX_PCI_IE 0x00000100 00103 # define PLX_PCI_DOORBELL_IE 0x00000200 00104 # define PLX_PCI_ABORT_IE 0x00000400 00105 # define PLX_PCI_LOCAL_IE 0x00000800 00106 # define PLX_RETRY_ABORT_ENABLE 0x00001000 00107 # define PLX_PCI_DOORBELL_INT 0x00002000 00108 # define PLX_PCI_ABORT_INT 0x00004000 00109 # define PLX_PCI_LOCAL_INT 0x00008000 00110 # define PLX_LCL_IE 0x00010000 00111 # define PLX_LCL_DOORBELL_IE 0x00020000 00112 # define PLX_LCL_DMA0_IE 0x00040000 00113 # define PLX_LCL_DMA1_IE 0x00080000 00114 # define PLX_LCL_DOORBELL_INT 0x00100000 00115 # define PLX_LCL_DMA0_INT 0x00200000 00116 # define PLX_LCL_DMA1_INT 0x00400000 00117 # define PLX_LCL_BIST_INT 0x00800000 00118 # define PLX_BM_DIRECT_ 0x01000000 00119 # define PLX_BM_DMA0_ 0x02000000 00120 # define PLX_BM_DMA1_ 0x04000000 00121 # define PLX_BM_ABORT_ 0x08000000 00122 # define PLX_MBOX0_INT 0x10000000 00123 # define PLX_MBOX1_INT 0x20000000 00124 # define PLX_MBOX2_INT 0x40000000 00125 # define PLX_MBOX3_INT 0x80000000 00126 00127 00128 #define PLX_CNTRL 0x6c /* EEPROM,PCI,User,Init Control/Status */ 00129 00130 # define PLX_PCI_DMA_RD_CMD(x) (((x) & 0xf) << 0) 00131 # define PLX_PCI_DMA_WR_CMD(x) (((x) & 0xf) << 4) 00132 # define PLX_PCI_DIRM_RD_CMD(x) (((x) & 0xf) << 8) 00133 # define PLX_PCI_DIRM_WR_CMD(x) (((x) & 0xf) << 12) 00134 # define PLX_USEROUT 0x00010000 00135 # define PLX_USERIN 0x00020000 00136 # define PLX_EECK 0x01000000 00137 # define PLX_EECS 0x02000000 00138 # define PLX_EEWD 0x04000000 00139 # define PLX_EERD 0x08000000 00140 # define PLX_EEPRESENT 0x10000000 00141 # define PLX_RELOAD_CONFIG 0x20000000 00142 # define PLX_PCI_SW_RESET 0x40000000 00143 # define PLX_LCL_INIT_STATUS 0x80000000 00144 00145 00146 #define PLX_PCIHIDR 0x70 // PCI Permanent Configuration ID Reg 00147 #define PLX_PCIHREV 0x74 // PCI Permanent Revision ID Reg 00148 00149 /* 00150 * DMA registers. Offset is from PCI side 00151 */ 00152 #define PLX_DMA0_MODE 0x80 00153 00154 # define PLX_DMA_MODE_WIDTH32 0x00000003 00155 # define PLX_DMA_MODE_WAITSTATES(x) (((x) & 0xf) << 2) 00156 # define PLX_DMA_MODE_NOREADY 0x00000000 00157 # define PLX_DMA_MODE_READY 0x00000040 00158 # define PLX_DMA_MODE_NOBTERM 0x00000000 00159 # define PLX_DMA_MODE_BTERM 0x00000080 00160 # define PLX_DMA_MODE_NOBURST 0x00000000 00161 # define PLX_DMA_MODE_BURST 0x00000100 00162 # define PLX_DMA_MODE_NOCHAIN 0x00000000 00163 # define PLX_DMA_MODE_CHAIN 0x00000200 00164 # define PLX_DMA_MODE_DONE_IE 0x00000400 00165 # define PLX_DMA_MODE_ADDR_HOLD 0x00000800 00166 # define PLX_DMA_MODE_DEMAND 0x00001000 00167 # define PLX_DMA_MODE_WR_AND_INVL 0x00002000 // write and invalidate 00168 # define PLX_DMA_MODE_EOT_EN 0x00004000 00169 # define PLX_DMA_MODE_STOP 0x00008000 00170 # define PLX_DMA_MODE_CLR_CNT_EN 0x00010000 00171 # define PLX_DMA_MODE_INTR_PCI 0x00020000 // deliver DMA intr to PCI side 00172 # define PLX_DMA_MODE_INTR_LOCAL 0x00000000 // deliver DMA intr to Local side 00173 00174 00175 #define PLX_DMA0_PCI_ADDR 0x84 /* non-chaining mode PCI address */ 00176 00177 #define PLX_DMA0_LCL_ADDR 0x88 /* non-chaining mode local address */ 00178 00179 #define PLX_DMA0_SIZE 0x8C /* non-chaining mode length */ 00180 00181 #define PLX_DMA0_DESCRIPTOR 0x90 00182 # define PLX_DMA_DESC_IS_PCI 0x00000001 // desc is in PCI addr space 00183 # define PLX_DMA_DESC_IS_LCL 0x00000000 // desc is in Local addr space 00184 # define PLX_DMA_DESC_EOC 0x00000002 00185 # define PLX_DMA_DESC_TC_IE 0x00000004 00186 # define PLX_DMA_DESC_TO_HOST 0x00000008 00187 # define PLX_DMA_DESC_TO_BOARD 0x00000000 00188 # define PLX_DMA_DESC_NEXTADDR 0xFFFFfff0 00189 00190 00191 // chaining mode dma descriptor entry 00192 // must be 4 u32 aligned 00193 00194 struct plx_dma_entry { 00195 u32 pci_addr; // PCI bus address 00196 u32 local_addr; // local (board) bus address 00197 u32 length; // bytes 00198 u32 next_and_flags; // low 4 bits same as PLX_DMA_DESC_xxxx 00199 }; 00200 00201 00202 #define PLX_DMA1_MODE 0x94 00203 #define PLX_DMA1_PCI_ADDR 0x98 00204 #define PLX_DMA1_LCL_ADDR 0x9c 00205 #define PLX_DMA1_SIZE 0xa0 00206 #define PLX_DMA1_DESCRIPTOR 0xa4 00207 00208 #define PLX_DMA0_CSR 0xa8 // N.B., 8 bit register 00209 #define PLX_DMA1_CSR 0xa9 // N.B., 8 bit register 00210 00211 # define PLX_DMA_CSR_ENABLE 0x00000001 00212 # define PLX_DMA_CSR_START 0x00000002 00213 # define PLX_DMA_CSR_ABORT 0x00000004 00214 # define PLX_DMA_CSR_CLR_INTR 0x00000008 00215 # define PLX_DMA_CSR_DONE 0x00000010 00216 00217 00218 #define PLX_DMA_ARB 0xac // same as PLX_MARBR 00219 00220 #define PLX_DMA_THRESH 0xb0 00221 00222 // message queue registers (not defined) 00223 00224 #endif /* _PLX9080_H_ */

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