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Classes | |
struct | plx_dma_entry |
Defines | |
#define | PLX_LCL_OFFSET 0x80 |
#define | PLX_LAS0RR 0x00 |
#define | PLX_LAS0BA 0x04 |
#define | PLX_MARBR 0x08 |
#define | PLX_BIGEND 0x0c |
#define | PLX_EROMRR 0x10 |
#define | PLX_EROMBA 0x14 |
#define | PLX_LBRD0 0x18 |
#define | PLX_DMRR 0x1c |
#define | PLX_DMLBAM 0x20 |
#define | PLX_DMLBAI 0x24 |
#define | PLX_DMPBAM 0x28 |
#define | PLX_DMCFGA 0x2c |
#define | PLX_LAS1RR 0xf0 |
#define | PLX_LAS1BA 0xf4 |
#define | PLX_LBRD1 0xf8 |
#define | PLX_MBOX0 0x40 |
#define | PLX_MBOX1 0x44 |
#define | PLX_MBOX2 0x48 |
#define | PLX_MBOX3 0x4c |
#define | PLX_MBOX4 0x50 |
#define | PLX_MBOX5 0x54 |
#define | PLX_MBOX6 0x58 |
#define | PLX_MBOX7 0x5c |
#define | PLX_P2LDBELL 0x60 |
#define | PLX_L2PDBELL 0x64 |
#define | PLX_INTCSR 0x68 |
#define | PLX_LSERR_ENABLE 0x00000001 |
#define | PLX_LSERR_PE 0x00000002 |
#define | PLX_SERR 0x00000004 |
#define | PLX_MBOX_IE 0x00000008 |
#define | PLX_PCI_IE 0x00000100 |
#define | PLX_PCI_DOORBELL_IE 0x00000200 |
#define | PLX_PCI_ABORT_IE 0x00000400 |
#define | PLX_PCI_LOCAL_IE 0x00000800 |
#define | PLX_RETRY_ABORT_ENABLE 0x00001000 |
#define | PLX_PCI_DOORBELL_INT 0x00002000 |
#define | PLX_PCI_ABORT_INT 0x00004000 |
#define | PLX_PCI_LOCAL_INT 0x00008000 |
#define | PLX_LCL_IE 0x00010000 |
#define | PLX_LCL_DOORBELL_IE 0x00020000 |
#define | PLX_LCL_DMA0_IE 0x00040000 |
#define | PLX_LCL_DMA1_IE 0x00080000 |
#define | PLX_LCL_DOORBELL_INT 0x00100000 |
#define | PLX_LCL_DMA0_INT 0x00200000 |
#define | PLX_LCL_DMA1_INT 0x00400000 |
#define | PLX_LCL_BIST_INT 0x00800000 |
#define | PLX_BM_DIRECT_ 0x01000000 |
#define | PLX_BM_DMA0_ 0x02000000 |
#define | PLX_BM_DMA1_ 0x04000000 |
#define | PLX_BM_ABORT_ 0x08000000 |
#define | PLX_MBOX0_INT 0x10000000 |
#define | PLX_MBOX1_INT 0x20000000 |
#define | PLX_MBOX2_INT 0x40000000 |
#define | PLX_MBOX3_INT 0x80000000 |
#define | PLX_CNTRL 0x6c |
#define | PLX_PCI_DMA_RD_CMD(x) (((x) & 0xf) << 0) |
#define | PLX_PCI_DMA_WR_CMD(x) (((x) & 0xf) << 4) |
#define | PLX_PCI_DIRM_RD_CMD(x) (((x) & 0xf) << 8) |
#define | PLX_PCI_DIRM_WR_CMD(x) (((x) & 0xf) << 12) |
#define | PLX_USEROUT 0x00010000 |
#define | PLX_USERIN 0x00020000 |
#define | PLX_EECK 0x01000000 |
#define | PLX_EECS 0x02000000 |
#define | PLX_EEWD 0x04000000 |
#define | PLX_EERD 0x08000000 |
#define | PLX_EEPRESENT 0x10000000 |
#define | PLX_RELOAD_CONFIG 0x20000000 |
#define | PLX_PCI_SW_RESET 0x40000000 |
#define | PLX_LCL_INIT_STATUS 0x80000000 |
#define | PLX_PCIHIDR 0x70 |
#define | PLX_PCIHREV 0x74 |
#define | PLX_DMA0_MODE 0x80 |
#define | PLX_DMA_MODE_WIDTH32 0x00000003 |
#define | PLX_DMA_MODE_WAITSTATES(x) (((x) & 0xf) << 2) |
#define | PLX_DMA_MODE_NOREADY 0x00000000 |
#define | PLX_DMA_MODE_READY 0x00000040 |
#define | PLX_DMA_MODE_NOBTERM 0x00000000 |
#define | PLX_DMA_MODE_BTERM 0x00000080 |
#define | PLX_DMA_MODE_NOBURST 0x00000000 |
#define | PLX_DMA_MODE_BURST 0x00000100 |
#define | PLX_DMA_MODE_NOCHAIN 0x00000000 |
#define | PLX_DMA_MODE_CHAIN 0x00000200 |
#define | PLX_DMA_MODE_DONE_IE 0x00000400 |
#define | PLX_DMA_MODE_ADDR_HOLD 0x00000800 |
#define | PLX_DMA_MODE_DEMAND 0x00001000 |
#define | PLX_DMA_MODE_WR_AND_INVL 0x00002000 |
#define | PLX_DMA_MODE_EOT_EN 0x00004000 |
#define | PLX_DMA_MODE_STOP 0x00008000 |
#define | PLX_DMA_MODE_CLR_CNT_EN 0x00010000 |
#define | PLX_DMA_MODE_INTR_PCI 0x00020000 |
#define | PLX_DMA_MODE_INTR_LOCAL 0x00000000 |
#define | PLX_DMA0_PCI_ADDR 0x84 |
#define | PLX_DMA0_LCL_ADDR 0x88 |
#define | PLX_DMA0_SIZE 0x8C |
#define | PLX_DMA0_DESCRIPTOR 0x90 |
#define | PLX_DMA_DESC_IS_PCI 0x00000001 |
#define | PLX_DMA_DESC_IS_LCL 0x00000000 |
#define | PLX_DMA_DESC_EOC 0x00000002 |
#define | PLX_DMA_DESC_TC_IE 0x00000004 |
#define | PLX_DMA_DESC_TO_HOST 0x00000008 |
#define | PLX_DMA_DESC_TO_BOARD 0x00000000 |
#define | PLX_DMA_DESC_NEXTADDR 0xFFFFfff0 |
#define | PLX_DMA1_MODE 0x94 |
#define | PLX_DMA1_PCI_ADDR 0x98 |
#define | PLX_DMA1_LCL_ADDR 0x9c |
#define | PLX_DMA1_SIZE 0xa0 |
#define | PLX_DMA1_DESCRIPTOR 0xa4 |
#define | PLX_DMA0_CSR 0xa8 |
#define | PLX_DMA1_CSR 0xa9 |
#define | PLX_DMA_CSR_ENABLE 0x00000001 |
#define | PLX_DMA_CSR_START 0x00000002 |
#define | PLX_DMA_CSR_ABORT 0x00000004 |
#define | PLX_DMA_CSR_CLR_INTR 0x00000008 |
#define | PLX_DMA_CSR_DONE 0x00000010 |
#define | PLX_DMA_ARB 0xac |
#define | PLX_DMA_THRESH 0xb0 |
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