#include <GrUsrpSource.h>
Inheritance diagram for GrUsrpSource:
Public Member Functions | |
GrUsrpSource (int which_board, unsigned int usrp_rx_config, unsigned int adc_clk_div, unsigned int decim_rate) | |
~GrUsrpSource () | |
GrUsrpSource * | make (int which_board, unsigned int usrp_rx_config, unsigned int adc_clk_div, unsigned int decim_rate) |
virtual const char * | name () |
default name for a module (override with actual name) | |
virtual int | work2 (VrSampleRange output, void *o[]) |
bool | set_adc_clk_div (unsigned int div) |
bool | set_decim_rate (unsigned int rate) |
bool | set_rx_freq (int channel, double freq) |
bool | set_ext_clk_div (unsigned int div) |
bool | _set_decim_reg (unsigned int regval) |
double | get_oscillator_freq () const |
unsigned int | get_adc_clk_div () const |
unsigned int | get_decim_rate () const |
double | get_rx_freq (int channel) const |
unsigned int | get_ext_clk_div () const |
Private Attributes | |
int | d_noutputs |
usrp_rx * | d_usrp |
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usrp_rx_config specifies which and how many of the four possible A/D streams will be read. adc_clk_div specifies the divisor used to divide down the on-board master clock (currently 125MHz, but will be 120MHz). Legal values are in the range 2 through 6, inclusive. The resulting clock drives the A/D converters. decim_rate specifies the decimation rate through the CIC filter associated with each rx channel in the FPGA. The output is N streams of VrComplex, where N is determined by the usrp_rx_config value. See usrp_config.h. |
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invoke constructor and return instance, or 0 if trouble |
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default name for a module (override with actual name)
Reimplemented from GrSource.
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Implements GrSource.
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