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Chapter 3  Circuit description

3.1  Summary

To describe a circuit, you must provide a `netlist'. The netlist is simply a list of the components with their connections and values. The format is essentially the same as the standard SPICE format.

Before doing this, number the nodes on your schematic. (A node is a place where parts connect together.) Then, each part gets a line in the netlist (circuit description). In its simplest form, which you will use most of the time, it is just the type, such as `R' for resistor, or a label, like `R47', followed by the two nodes it connects to, then its value.

Example: `R29 6 8 22k' is a 22k resistor between nodes 6 and 8.

ground node common node voltage reference Node 0 is used as a reference for all calculations and is assumed to have a voltage of zero. (This is the ground, earth or common node.) Nodes must be nonnegative integers, but need not be numbered sequentially.

open circuit error There should be a DC path through the circuit to node 0 from every node that is actually used. The circuit cannot contain a cutset of current sources and/or capacitors. If either of these cases occurs, it will be discovered during analysis. The program will attempt to correct the error, issue an `open circuit' error message and continue. This is rarely a problem with real circuits. Most circuits have such a path, however indirect.

Semiconductor devices require both a device statement, and a .model statement (or ``card''). The device statement, described in the Circuit description chapter, defines individual devices as variations from a prototype, as is required for different devices on the same substrate. The model statement, described in this chapter, defines process dependent parameters, which usually apply to all devices on a substrate.

The .model card syntax is: .model mname type {args}

Mname is the model name, which elements will use to refer to this model. Type is one of several types of built-in models. Args is a list of the parameters, of the form name=value.
D
Diode model

NMOS
N-channel MOSFET model

PMOS
P-channel MOSFET model

LOGIC
Logic family description

SW
Voltage controlled switch

CSW
Current controlled switch

C
Semiconductor capacitor

R
Semiconductor resistor

TABLE
y/x table of values

3.2  C: Capacitor

3.2.1  Syntax

Cxxxxxxx n+ n-- value
Cxxxxxxx n+ n-- expression
Cxxxxxxx n+ n-- value {IC=initial-voltage}
Cxxxxxxx n+ n-- model {L=length} {W=width} {TEMP=temperature} {IC=initial-voltage}
.CAPacitor label n+ n-- expression

3.2.2  Purpose

Capacitor, or general charge storage element.

3.2.3  Probes

The following probes (Transient, DC, and OP analysis) are available in addition to those available for all basic elements.
DT
Time step. The internal time step used for this device for numerical integration. It is not necessarily the same as the global time step.

TIME
Time. The time of the most recent calculation of this device. It is not necessarily the same as the global time.

TIMEOLD
The time of the previous calculation of this device. It is not necessarily the same as the global time.

TIMEFuture
The latest recommended time for the next sample, as determined by this device. The actual time will probably be sooner than this.

CHarge
The charge stored in this capacitor.

Q
The same as Charge.

Capacitance
The effective capacitance of this device. For a fixed capacitor, it is constant. It will vary if this device is nonlinear.

DQDT
The time derivative of charge. Hopefully this is the same as current, but it is calculated a different way and can be used as an accuracy check.

DQ
The change in charge compared to the previous sample. Its primary use is in debugging models and numerical problems.

3.2.4  Comments

N+ and n-- are the positive and negative element nodes, respectively. Value is the capacitance in Farads.

The (optional) initial condition is the initial (time = 0) value of the capacitor voltage (in Volts). Note that the initial conditions (if any) apply only if the UIC option is specified on the transient command.

You may specify the value in one of three forms:
  1. A simple value. This is the capacitance in Farads.

  2. An expression, as described in the behavioral modeling chapter. The expression can specify the charge as a function of voltage, or the capacitance as a function of time.

  3. A model, which calculates the capacitance as a function of length and width, referencing a .model statement of type C. This is compatible with the Spice-3 ``semiconductor capacitor''.

3.2.5  Model statement

A model statement may be used,, with model type C or Cap. The parameters are:
CJ = x
Junction bottom capacitance. (Farads / meter squared). (Default = 0.)

CJSW = x
Junction sidewall capacitance. (Farads / meter). (Default = 0.)

DEFW = x
Default width. (meters). (Default = 1e-6)

NARROW = x
Narrowing due to side etching. (meters). (Default = 0.)

TC1 = x
First order temperature coefficient. (Farads / degree C). (Default = 0.) (Not in Spice.)

TC2 = x
Second order temperature coefficient. (Farads / degree C squared). (Default = 0.) (Not in Spice.)

TNOM = x
Parameter measurement temperature. (degrees C.). (Default = 27.) (Not in Spice.)
Capacitance is computed by the formula:
capacitance = CJ * (L - NARROW) * (W - NARROW)
  + 2 * CJSW * (L + L - 2 * NARROW)
After the nominal value is calculated, it is adjusted for temperature by the formula:
value *= (1 + TC1 * (T-T0) + TC2 * (T-T0)^2)

3.3  Trans-capacitor

3.3.1  Syntax

.TCAPacitor label n+ n-- nc+ nc-- expression
.TCAPacitor label n+ n-- nc+ nc-- value {IV=initial-voltage}
.TCAPacitor label n+ n-- model {L=length} {W=width} {IC=initial-voltage}

3.3.2  Purpose

Trans-capacitor, or charge transfer device.

3.3.3  Probes

All probes that apply to ordinary capacitors also apply here.

3.3.4  Comments

N+ and n-- are the positive and negative element nodes, respectively. Nc+ and nc-- are the positive and negative controlling nodes, respectively.

This device places a charge between the output nodes that depends on the voltage on its input nodes. If you parallel the input with the output, it becomes an ordinary capacitor. While the use of this device may appear straightforward, be careful. It is easy to use it in an unstable way.

All options, expressions, models, and probes that apply to ordinary capacitors can also be used here.

It is used internally in some transistor models.

3.4  D: Diode

3.4.1  Syntax

Dxxxxxxx n+ n-- mname {area} {args}
.DIOde xxxxxxx n+ n-- mname {area} {args}

3.4.2  Purpose

Junction diode.

3.4.3  Comments

N+ and n-- are the positive and negative element nodes, respectively. Mname is the model name. Area is the area factor. If the area factor is omitted, a value of 1.0 is assumed. Args is a list of additional arguments. The parameters available are a superset of those available in SPICE.

A diode can also use a MOSFET model (type NMOS or PMOS) to represent the equivalent of the source-bulk or drain-bulk diodes.

When the element is printed out, by a list or save command, the the computed values of IS, RS, CJ, and CJSW are printed as a comment if they were not explicitly entered.

3.4.4  Element Parameters

Area = x
Area factor. (Default = 1.0) If optional parameters IS, RS, and CJO are not specified, the .model value is multiplied by area to get the actual value.

Perim = x
Perimeter factor. (Default = 1.0) If optional parameter CJSW is not specified, the .model value is multiplied by perim to get the actual value.

IC = x
Initial condition. The initial voltage to use in transient analysis, if the UIC option is specified. Default: don't use initial condition. This is presently ignored, but accepted for compatibility.

OFF
Start iterating with this diode off, in DC analysis.

IS = x
Saturation current. This overrides IS in the .model, and is not affected by area. Default: use IS from .model * area.

RS = x
Ohmic (series) resistance. This overrides RS in the .model, and is not affected by area. Default: use RS from .model * area.

CJ = x
Zero-bias junction capacitance. This overrides CJ in the .model, and is not affected by area. Default: use CJ from .model * area.

CJSW = x
Zero-bias sidewall capacitance. This overrides CJSW in the .model, and is not affected by perim. Default: use CJSW from .model * perim.

GParallel = x
Parallel conductance. This overrides GParallel in the .model, and is not affected by area. Default: use GParallel from .model * area.

3.4.5  Model Parameters

IS = x
Normalized saturation current. (Amperes). (Default = 1.0e-14) IS is multiplied by the area in the element statement to get the actual saturation current. It may be overridden by specifying IS in the element statement.

RS = x
Normalized ohmic resistance. (Ohms) (Default = 0.) RS is multiplied by the area in the element statement to get the actual ohmic resistance. It may be overridden by specifying RS in the element statement.

N = x
Emission coefficient. (Default = 1.0) In ECA-2 the default value was 2.

TT = x
Transit time. (Default = 0.) The diffusion capacitance is given by: cd = TT gd where gd is the diode conductance.

VJ = x
Junction potential. (Default = 1.0) Used in computation of capacitance. For compatibility with older versions of SPICE, PB is accepted as an alias for VJ.

CJo = x
Normalized zero-bias depletion capacitance. (Default = 0.) CJo is multiplied by the area in the element statement to get the actual zero-bias capacitance. It may be overridden by specifying CJ in the element statement.

Mj = x
Grading coefficient. (Default = 0.5)

PBSw = x
Sidewall junction potential. (Default = PB)

CJSw = x
Normalized zero-bias sidewall capacitance. (Default = 0.) CJSw is multiplied by the perimeter in the element statement to get the actual zero-bias capacitance. It may be overridden by specifying CJSW in the element statement.

MJSw = x
Sidewall grading coefficient. (Default = 0.33)

EG = x
Activation energy. (electron Volts) (Default = 1.11, silicon.) For other types of diodes, use: 1.11 ev. Silicon (default value)
0.69 ev. Schottky barrier
0.67 ev. Germanium
1.43 ev. GaAs
2.26 ev. GaP

XTI = x
Saturation current temperature exponent. (Default = 3.0) For Schottky barrier, use 2.0.

KF = x
Flicker noise coefficient. (Default = 0.) SPICE parameter accepted but not implemented.

AF = x
Flicker noise exponent. (Default = 1.0) SPICE parameter accepted but not implemented.

FC = x
Coefficient for forward bias depletion capacitance formula. (Default = 0.5)

BV = x
Reverse breakdown voltage. (Default = ¥.) SPICE parameter accepted but not implemented.

IBV = x
Current at breakdown voltage. (Default = 1 ma.) SPICE parameter accepted but not implemented.

GParallel = x
Parallel conductance. (Default = 0.)

3.4.6  Probes

Vd
Voltage. The first node (anode) is assumed positive.

Id
Total current. It flows into the first node (anode), out of the second (cathode). I(Dxxxx) is the same as IJ(Dxxxx) + IC(Dxxxx).

VJ
Junction voltage. The voltage across the junction, excluding the series resistance.

VSR
Resistive voltage. The voltage across the series resistance, excluding the junction voltage.

IJ
Junction current. The current through the junction. IJ(Dxxxx) is the same as I(Yj.Dxxxx).

IC
Capacitor current. The current through the parallel capacitor. IC(Dxxxx) is the same as I(Cj.Dxxxx).

P
Power. P(Dxxxx) is the same as PJ(Dxxxx) + PC(Dxxxx).

PD
Power dissipated. The power dissipated as heat. It is always positive and does not include power sourced. It should be the same as P because the diode is passive.

PS
Power sourced. The power sourced by the part. It is always positive and does not consider its own dissipation. It should be 0 because the diode is passive.

PJ
Junction power. PJ(Dxxxx) is the same as P(Yj.Dxxxx).

PC
Capacitor power. PC(Dxxxx) is the same as P(Cj.Dxxxx).

Capacitance
Effective capacitance. C(Dxxxx) is the same as Capacitance(Cj.Dxxxx).

Req
Effective resistance. R(Dxxxx) is the same as R(Yj.Dxxxx).

Z
Impedance at a port. The port impedance seen looking into the circuit across the branch. It does not include the part itself. In transient analysis, it shows the effective Z-domain impedance, which is a meaningless number if there are capacitors or inductors in the circuit. (DC only)

ZRAW
Impedance at a port, raw. This is the same as ``Z'' except that it includes the part itself. (DC only)

REgion
Region code. A numeric code that represents the region it is operating in. +1 = forward, -1 = reversed, 0 = unknown, -2 = assumed off.
All parameters of the internal elements Yj and Cj are available. To access them, concatenate the labels for the internal element with the diode, separated by a dot. Yj.D6 is the admittance (Yj) element of the diode D6.

In this release, there are no probes available in AC analysis except for the internal elements.

The general element probes do not apply to diodes.

3.5  E: Voltage Controlled Voltage Source

3.5.1  Syntax

Exxxxxxx n+ n-- nc+ nc-- value
Exxxxxxx n+ n-- nc+ nc-- expression
.VCVS label n+ n-- nc+ nc-- expression

3.5.2  Purpose

Voltage controlled voltage source, or voltage gain block.

3.5.3  Comments

N+ and n-- are the positive and negative element (output) nodes, respectively. Nc+ and nc-- are the positive and negative controlling nodes, respectively. Value is the voltage gain.

3.6  F: Current Controlled Current Source

3.6.1  Syntax

Fxxxxxxx n+ n-- ce value
Fxxxxxxx n+ n-- ce expression
.CCCS label n+ n-- ce expression

3.6.2  Purpose

Current controlled current source, or current gain block.

3.6.3  Comments

N+ and n-- are the positive and negative element (output) nodes, respectively. Current flow is from the positive node, through the source, to the negative node. Ce is the name of an element through which the controlling current flows. The direction of positive controlling current is from the positive node, through the element, to the negative node of ce. Value is the transconductance in mhos.

The controlling element can be any simple two terminal element. Unlike SPICE, it does not need to be a voltage source.

3.7  G: Voltage Controlled Current Source

3.7.1  Syntax

Gxxxxxxx n+ n-- nc+ nc-- value
Gxxxxxxx n+ n-- nc+ nc-- expression
.VCCS label n+ n-- nc+ nc-- expression

3.7.2  Purpose

Voltage controlled current source, or transconductance block.

3.7.3  Comments

N+ and n-- are the positive and negative element (output) nodes, respectively. Current flow is from the positive node, through the source, to the negative node. Nc+ and nc-- are the positive and negative controlling nodes, respectively. Value is the transconductance in mhos.

The letter G can also be used to select the vccap, vcr, and vcg devices using a syntax compatible with some other simulators.

3.8  Voltage Controlled Capacitor

3.8.1  Syntax

Preferred syntax:
.VCCAP label n+ n-- nc+ nc-- expression
Alternate syntax:
Gxxxxxxx n+ n-- VCCAP nc+ nc-- expression

3.8.2  Purpose

Voltage controlled capacitor.

3.8.3  Probes

All probes that apply to ordinary capacitors also apply here.

3.8.4  Comments

N+ and n-- are the positive and negative element (output) nodes, respectively. Nc+ and nc-- are the positive and negative controlling nodes, respectively. Value is the transfactor in Farads per volt.

The simulator will faithfully give you a negative capacitor if it seems appropriate. Usually, this part is used with a behavioral modeling function, like PWL, which allows you to specify a table of capacitance vs. voltage.

3.9  Voltage Controlled Admittance

3.9.1  Syntax

Preferred syntax:
.VCG label n+ n-- nc+ nc-- expression
Alternate syntax:
Gxxxxxxx n+ n-- VCG nc+ nc-- expression

3.9.2  Purpose

Voltage controlled admittance.

3.9.3  Comments

N+ and n-- are the positive and negative element (output) nodes, respectively. Nc+ and nc-- are the positive and negative controlling nodes, respectively. Value is the transfactor in mhos per volt.

The simulator will faithfully give you a negative admittance if it seems appropriate. Usually, this part is used with a behavioral modeling function, like PWL, which allows you to specify a table of admittance vs. voltage.

3.10  Voltage Controlled Resistor

3.10.1  Syntax

Preferred syntax:
.VCR label n+ n-- nc+ nc-- expression
Alternate syntax:
Gxxxxxxx n+ n-- VCR nc+ nc-- expression

3.10.2  Purpose

Voltage controlled resistor.

3.10.3  Comments

N+ and n-- are the positive and negative element (output) nodes, respectively. Nc+ and nc-- are the positive and negative controlling nodes, respectively. Value is the transfactor in ohms per volt.

The simulator will faithfully give you a negative resistor if it seems appropriate. Usually, this part is used with a behavioral modeling function, like PWL, which allows you to specify a table of resistance vs. voltage.

3.11  H: Current Controlled Voltage Source

3.11.1  Syntax

Hxxxxxxx n+ n-- ce value
Hxxxxxxx n+ n-- ce expression
.CCVS label n+ n-- ce expression

3.11.2  Purpose

Current controlled voltage source, or transresistance block.

3.11.3  Comments

N+ and n-- are the positive and negative element (output) nodes, respectively. Ce is the name of an element through which the controlling current flows. The direction of positive controlling current is from the positive node, through the element, to the negative node of ce. Value is the transresistance in Ohms.

The controlling element can be any simple two terminal element. Unlike SPICE, it does not need to be a voltage source.

3.12  I: Independent Current Source

3.12.1  Syntax

Ixxxxxxx n+ n-- value
Ixxxxxxx n+ n-- expression
.ISOurce label n+ n-- expression

3.12.2  Purpose

Independent current source.

3.12.3  Comments

N+ and n-- are the positive and negative element nodes, respectively. Positive current flow is from the positive node, through the source, to the negative node. Value is the current in Amperes.

All of the SPICE time dependent functions (pulse, sin, exp, pwl, and sffm are supported. An additional function generator emulates a laboratory type function generator, for a more convenient signal input to the circuit.

3.13  J: Junction Field-Effect Transistor

3.13.1  Syntax

Jxxxxxxx nd ng ns mname {area} {args}

3.13.2  Purpose

Junction Field Effect Transistor.

3.13.3  Comments

Not implemented. Plans are to implement it as in SPICE.

3.14  K: Coupled (Mutual) Inductors

3.14.1  Syntax

Kxxxxxxx Lyyyyyyy Lzzzzzzz value
.MUTual_inductor label Lyyyyyyy Lzzzzzzz value

3.14.2  Purpose

Coupled mutual inductance.

3.14.3  Comments

K couples two inductors. The value is the coefficient of coupling. Using the dot convention, place a dot on the first node of each inductor.

The coefficient of coupling is given by K = Mij/Li Lj.

3.14.4  Bugs

This release does not support multiple coupled inductors.

3.15  L: Inductor

3.15.1  Syntax

Lxxxxxxx n+ n-- value
Lxxxxxxx n+ n-- expression
Lxxxxxxx n+ n-- value {II=initial-current}
.INDuctor label n+ n-- expression

3.15.2  Purpose

Inductor, or general flux storage element.

3.15.3  Probes

The following probes are available in addition to those available for all basic elements.
DT
Time step. The internal time step used for this device for numerical integration. It is not necessarily the same as the global time step.

TIME
Time. The time of the most recent calculation of this device. It is not necessarily the same as the global time.

TIMEOLD
The time of the previous calculation of this device. It is not necessarily the same as the global time.

3.15.4  Comments

N+ and n-- are the positive and negative element nodes, respectively. Value is the inductance in Henries.

The (optional) initial condition is the initial (time = 0) value of the inductor current (in Amperes). Note that the initial conditions (if any) apply only if the UIC option is specified on the transient command.

3.16  M: MOSFET

3.16.1  Syntax

Mxxxxxxx nd ng ns nb mname {args}
Mxxxxxxx nd ng ns nb mname {width/length} {args}
.MOSfet label nd ng ns nb mname {args}
.MOSfet label nd ng ns nb mname {width/length} {args}

3.16.2  Purpose

MOSFET.

3.16.3  Comments

Nd, ng, ns, and nb are the drain, gate, source, and bulk (substrate) nodes, respectively. Mname is the model name.

Length and width are the drawn channel length and width, in microns. Note that the notation W/L has units of microns, but the same parameters, in the argument list (W and L) have units of meters. All other dimensions are in meters.

The options rstray and norstray determines whether or not series resistances are included. rstray is the default. Experience has shown that the effect of series resistance is often not significant, it can significantly degrade the simulation time, and it often increases roundoff errors. rstray is the default for Spice compatibility, and because it usually is significant for the BJT model. Norstray is the equivalent of setting the model parameters rd, rs, and rsh all to zero.

Entering a parameter value of 0 is not the same as not specifying it. This behavior is not compatible with SPICE. In SPICE, a value of 0 is often interpreted as not specified, with the result being to calculate it some other way. If you want it to be calculated, don't specify it.

Another subtle difference from SPICE is that Gnucap may omit some unnecessary parts of the model, which may affect some reported values. It should not affect any voltages or currents. For example, if the gate and drain are tied, Cgs will be omitted from the model, so the printed value for Cgdovl and Cgd will be 0, which will disagree with SPICE. It doesn't matter because a shorted capacitor can store no charge.

Levels 1, 2, 3, 4, 5, 6, 7 are implemented.

3.16.4  Element Parameters

Basic Spice compatible parameters

L = x
Drawn channel length. (Default = DEFL parameter from options. DEFL default = 100µ)

W = x
Drawn channel width. (Default = DEFW parameter from options. DEFW default = 100µ)

AD = x
Area of drain diffusion. (Default = DEFAD parameter from options. DEFAD default = 0)

AS = x
Area of source diffusion. (Default = DEFAS parameter from options. DEFAS default = 0)

PD = x
Perimeter of drain junction. (Default = 0.)

PS = x
Perimeter of source junction. (Default = 0.)

NRD = x
Number of squares of drain diffusion. (Default = 1.)

NRS = x
Number of squares of source diffusion. (Default = 1.)

3.16.5  Model Parameters

Basic selection -- required for all models

LEVEL = x
Model index. (Default = 1) Selects which of several models to use. The choices supported are 1-7, corresponding to Spice 3f5.

Extended control (not in Spice) -- all models

CMODEL = x
Capacitance model selector (Default = 1 for level 4,5,7. Default = 2 for level 1,2,3. Default = 3 for level 6.) The only valid values are 1, 2 and 3. 2 selects Meyer capacitance calculations compatible with Spice 2. 3 selects Meyer's model compatible with Spice 3. 1 selects not to use Meyer's model.

Binning (not in Spice) -- all models

Gnucap supports ``binning''. You can specify any number of models as a family. These models must have the selection parameters WMAX, WMIN, LMAX, and LMIN.

To use ``binning'', define a set of models with the same name, except for a numeric extension, beginning at 1. The models must be numbered consecutively. For example, you might have a set of models: NM3U.1, NM3U.2, NM3U.3, NM3U.4, NM3U.5, NM3U.6. For the device, you would specify the model NM3U. The first model meeting the requirements that length is between LMIN and LMAX, and width is between WMIN and WMAX will be used. They will be tried in numerical order.

If there is a gap in the numbering, only those below the gap will be used. If you want a specific model from a set, disabling binning, you can specify its full name.
WMAX = x
Maximum width. (Default = Infinity.) The maximum device width that may be used with this model.

WMIN = x
Maximum width. (Default = 0.) The minimum device width that may be used with this model.

LMAX = x
Maximum length. (Default = Infinity.) The maximum device length that may be used with this model.

LMIN = x
Maximum length. (Default = 0.) The minimum device length that may be used with this model.

Substrate coupling -- all models

IS = x
Bulk junction saturation current. If not input, it is calculated from JS. If both are input, a warning is issued, and the calculated value (from JS) is used, if AD and AS are also input. If neither IS or JS is input, a default value of 1e-14 is used.

JS = x
Bulk junction saturation current per square-meter of junction area. May be used to calculate IS. If a conflict exists, a warning is issued.

FC = x
Coefficient for forward bias depletion capacitance formula. (Default = 0.5)

PB = x
Bulk junction potential. (Default = 0.8)

CJ = x
Zero bias bulk junction bottom capacitance per square-meter of junction area. If not input, but NSUB is, it is calculated, otherwise a default value of 0 is used.

MJ = x
Bulk junction bottom grading coefficient. (Default = 0.5)

PBSW = x
Sidewall Bulk junction potential. (Default = PB)

CJSW = x
Zero bias bulk junction sidewall capacitance per meter of junction perimeter. (Default = 0.)

MJSW = x
Bulk junction sidewall grading coefficient. (Default = 0.33)

Strays -- all models

RSH = x
Drain and source diffusion sheet resistance. If not input, use RS and RD directly. If a conflict exists, a warning is issued. The resistance is only used if the option rstray is set.

RD = x
Drain ohmic resistance (unscaled). If RS is input, the default value of RD is 0. If RD and RS are both not input, and RSH is input, they are calculated from RSH. If any conflict exists, a warning is issued, indicating the action taken, which is believed to be compatible with SPICE. The resistance is only used if the option rstray is set.

RS = x
Source ohmic resistance (unscaled). If RD is input, the default value of RS is 0. If RD and RS are both not input, and RSH is input, they are calculated from RSH. If any conflict exists, a warning is issued, indicating the action taken, which is believed to be compatible with SPICE. The resistance is only used if the option rstray is set.

CBD = x
Zero bias B-D junction capacitance (unscaled). If CBD is not specified, it is calculated from CJ.

CBS = x
Zero bias B-S junction capacitance (unscaled). If CBS is not specified, it is calculated from CJ.

CGSO = x
Gate-source overlap capacitance, per channel width. (Default = 0.)

CGDO = x
Gate-drain overlap capacitance, per channel width. (Default = 0.)

CGBO = x
Gate-bulk overlap capacitance, per channel length. (Default = 0.)

Accepted and ignored -- all models

KF = x
Flicker noise coefficient. SPICE parameter accepted but not implemented.

AF = x
Flicker noise exponent. SPICE parameter accepted but not implemented.

Level 1,2,3,6 shared parameters

VTO = x
Zero bias threshold voltage. If not input, but NSUB is, it is calculated, otherwise a default value of 0 is used.

KP = x
Transconductance parameter. If not input, it is calculated by UO * COX.

GAMMA = x
Bulk threshold parameter. If not input, but NSUB is, it is calculated, otherwise a default value of 0 is used.

PHI = x
Surface potential. If not input, but NSUB is, it is calculated, otherwise a default value of 0.6 is used. A warning is issued if the calculated value is less than 0.1, in which case 0.1 is used.

LAMBDA = x
Channel length modulation. If not input, it is calculated dynamically during simulation. If the value input is larger than 0.2, a warning is issued, but no correction is made. (accepted but ignored for level 3)

TOX = x
Oxide thickness. (meters) (Default = 1e-7)

NSUB = x
Substrate doping. (atoms / cm3) Used in calculation of VTO, GAMMA, PHI, and CJ. If not input, default values are used.

NSS = x
Surface state density. (atoms / cm2) (Default = 0.) Used, with NSUB in calculation of VTO.

XJ = x
Metallurgical junction depth. (meters) Used to calculate short channel effects. If not input, do not model short channel effects, effectively defaults to 0.

LD = x
Lateral diffusion. (Default = 0.) Effective channel length is reduced by 2 * LD.

UO = x
Surface mobility. (cm2/V-s) (Default = 600.)

DELTA = x
Width effect on threshold voltage. (Default = 0.) (Level 2 and 3 only.)

TPG = x
Type of gate material. (Default = 1.) +1 opposite to substrate
--1 same as substrate
0 Aluminum

Level 1

The Level 1 model has no additional parameters.

Level 2

NFS = x
Fast surface state density. (atoms / cm2) Used in modeling sub-threshold effects. If not input, do not model sub-threshold effects.

VMAX = x
Maximum drift velocity of carriers. (m/s) Used in calculating vdsat, and lambda. If not input, use a different method. VMAX does not always work, if the method fails, the alternate method is used and the warning ``Baum's theory rejected'' is issued if the error threshold is set to debug or worse.

NEFF = x
Total channel charge (fixed and mobile) coefficient. (Default = 1.) Used in internal calculation of lambda.

UCRIT = x
Critical field for mobility degradation. (V/cm) (Default = 1e4)

UEXP = x
Critical field exponent in mobility degradation. If not input, do not model mobility degradation, effectively defaulting to 0.

UTRA = x
Transverse field coefficient. SPICE parameter accepted but not implemented. It is also not implemented in most versions of SPICE.

Level 3

NFS = x
Fast surface state density. (atoms / cm2) Same as Level 2.

VMAX = x
Maximum drift velocity of carriers. (m/s) Used in calculating vdsat. If not input, use a different method.

THETA = x
Mobility modulation.

ETA = x
Static feedback.

KAPPA = x
Saturation field vector.

Level 6

KV = x
Saturation voltage factor.

NV = x
Saturation voltage coefficient.

KC = x
Saturation current factor.

NC = x
Saturation current coefficient.

NVTH = x
Threshold voltage coefficient.

PS = x
Sat. current modification par.

GAMMA1 = x
Bulk threshold parameter 1.

SIGMA = x
Static feedback effect par.

LAMBDA1 = x
Channel length modulation parameter. 1.

Level 4, 5, 7, 8 (BSIM models) general comments

The BSIM models have additional parameters for length, width, and product (length * width) dependency. To get the name, prefix the listed parameter with L, W, or P, respectively. Spice supports the ``P'' parameter only for BSIM3, but Gnucap supports it for all 3 models. For example, VFB is the basic parameter with units of Volts, and LVFB, WVFB, and PVFB also exist. The units of LVFB and WVFB are Volts * micron. The units of PVFB are Volts * micron * micron. The real parameter is calculated by P = P0 + PL / L + PW / W + PP / (L*W), where L and W are the effective length and width in microns.

The parameter s are not listed here, but they are the same as Spice 3f5, with the same defaults.

The ``levels'' are the same as Spice.
4
BSIM 1.
5
BSIM 2.
7
BSIM 3v3.1.
The following are reserved for future use:
8
BSIM 3v3.2.
9
BSIM-SOI.
10
BSIM 4.

3.16.6  Probes

VDS
Drain-source voltage.

VGS
Gate-source voltage.

VBS
Bulk-source voltage.

VDSInt
Drain-source internal voltage.

VGSInt
Gate-source internal voltage.

VBSInt
Bulk-source internal voltage.

VGD
Gate-drain voltage.

VBD
Bulk-drain voltage.

VSD
Source-drain voltage.

VDM
Drain-midpoint voltage.

VGM
Gate-midpoint voltage.

VBM
Bulk-midpoint voltage.

VSM
Source-midpoint voltage.

VDG
Drain-gate voltage.

VBG
Bulk-gate voltage.

VSG
Source-gate voltage.

VDB
Drain-bulk voltage.

VGB
Gate-bulk voltage.

VSB
Source-bulk voltage.

VD
Drain-ground voltage.

VG
Gate-ground voltage.

VB
Bulk-ground voltage.

VS
Source-ground voltage.

Id
Drain current.

IS
Source current.

IG
Gate current.

IB
Bulk current.

CGSO
Gate-source overlap capacitance.

CGDO
Gate-drain overlap capacitance.

CGBO
Gate-bulk overlap capacitance.

CGSm
Gate-source Meyer capacitance.

CGDm
Gate-drain Meyer capacitance.

CGBm
Gate-bulk Meyer capacitance.

CGST
Gate-source total capacitance.

CGDT
Gate-drain total capacitance.

CGBT
Gate-bulk total capacitance.

CBD
Bulk-drain junction capacitance.

CBS
Bulk-source junction capacitance.

CGATE
Nominal gate capacitance.

GM
Transconductance.

GDS
Drain-source conductance.

GMB
Body effect transconductance.

VDSAT
Saturation voltage.

VTH
Threshold voltage.

IDS
Drain-source current, not including strays.

IDSTray
Drain current due to strays.

IError
Estimated drain current error bound.

P
Power.

PD
Power dissipated. The power dissipated as heat. It is always positive and does not include power sourced. It should be the same as P because the mosfet cannot generate energy.

PS
Power sourced. The power sourced by the part. It is always positive and does not consider its own dissipation. It should be 0 because the mosfet cannot generate energy.

REgion
Region code. A numeric code that represents the region it is operating in. The number is the sum of several factors. A negative code indicates the source and drain are reversed.
1 Active. (Not cut off.)

2 Not sub-threshold.

4 Saturated.

10 Source to bulk is forward biased.

20 Drain to bulk is forward biased.

40 Punch through.
All parameters of the internal elements (Ids, Gmr, Gmf, Yds, Gmbr, Gmbf, Cgb, Cgd, Cgs, Dsb, Ddb, Rd, Rs) are available. To access them, concatenate the labels for the internal element with this device, separated by a dot. Cgd.M6 is the gate to drain capacitance of M6.

In this release, there are no probes available in AC analysis except for the internal elements.

3.17  Q: Bipolar Junction Transistor

3.17.1  Syntax

Qxxxxxxx nc nb ne ns mname {area} {args}
.BJT label nc nb ne ns mname {area} {args}

3.17.2  Purpose

Bipolar junction transistor,

3.17.3  Comments

Nc, nb, ne, and ns are the collector, base, emitter, and substrate nodes, respectively. Mname is the model name.

Area is a unit-less multiplier for the area.

The options rstray and norstray determines whether or not series resistances are included. rstray is the default. Norstray is the equivalent of setting the model parameters rc, re, and rb all to zero.

Entering a parameter value of 0 is not the same as not specifying it. This behavior is not compatible with SPICE. In SPICE, a value of 0 is often interpreted as not specified, with the result being to calculate it some other way. If you want it to be calculated, don't specify it.

Another subtle difference from SPICE is that Gnucap may omit some unnecessary parts of the model, which may affect some reported values. It should not affect any voltages or currents. For example, if the gate and drain are tied, Cgs will be omitted from the model, so the printed value for Cgdovl and Cgd will be 0, which will disagree with SPICE. It doesn't matter because a shorted capacitor can store no charge.

3.17.4  Element Parameters

Basic Spice compatible parameters

Area = x
Junction area. (Default = 1) This is a scaling parameter, with no relevant actual units.

OFF
(Default = not specified) If this word is specified, the initial guess will assume the device is off.

TEMP = x
Junction temperature. (Default = the global temperature.)

ICVBE = x
Initial condition, Vbe. (Default = NA) Use this as the initial condition, when the UIC option is specified. The syntax is different from Spice, but the function is the same.

ICVCE = x
Initial condition, Vce. (Default = NA) Use this as the initial condition, when the UIC option is specified. The syntax is different from Spice, but the function is the same.

3.17.5  Model Parameters

Basic DC parameters

BF = x
Ideal maximum forward beta. (Default = 100) Alternate name is BFM.

BR = x
Ideal maximum reverse beta. (Default = 1) Alternate name is BRM.

IBC = x
BC Transport saturation Current per area. (Default = IS) If omitted, IS is used. You should specify either IS or IBC, not both.

IBE = x
BE Transport saturation Current per area. (Default = IS) If omitted, IS is used. You should specify either IS or IBE, not both.

IS = x
Transport saturation Current per area. (Default = 1e-16) If IBE and IBC are specified, they are used instead. Do not specify both.

NF = x
Forward current emission coefficient. (Default = 1)

NR = x
Reverse current emission coefficient. (Default = 1)

Base width modulation

VAF = x
Forward Early voltage. (Default = Infinite) Alternate names are VA and VBF.

VAR = x
Reverse Early voltage. (Default = Infinite) Alternate name is VB.

Low current beta degeneration

ISC = x
B-C leakage saturation current. (Default = c4 * is)

C4 = x
B-C leakage scale factor. (Default = 0) Alternate name is JLC.

NC = x
B-C leakage emission coefficient. (Default = 2)

ISE = x
B-E leakage saturation current. (Default = c2 * is)

C2 = x
B-E leakage scale factor. (Default = 0) Alternate name is JLE.

NE = x
B-E leakage emission coefficient. (Default = 1.5)

High current beta degeneration

IKF = x
Forward beta roll-off corner current. (Default = Infinite) Alternate names are JBF and IK.

IKR = x
Reverse beta roll-off corner current. (Default = Infinite) Alternate name is JBR.

Parasitic resistance

IRB = x
Current for base resistance=(rb+rbm)/2". (Default = Infinite) Current where base resistance falls halfway to its minimum value. Alternate name is JRB.

RB = x
Zero bias base resistance. (Default = 0)

RBM = x
Minimum base resistance at high current. (Default = rb)

RE = x
Emitter resistance. (Default = 0)

RC = x
Collector resistance. (Default = 0)

Junction capacitance

CJC = x
Zero bias B-C depletion capacitance. (Default = 0)

CJE = x
Zero bias B-E depletion capacitance. (Default = 0)

CJS = x
Zero bias C-S capacitance. (Default = 0) Alternate name is CCS.

FC = x
Coefficient for forward-bias depletion capacitance formula. (Default = .5)

MJC = x
B-C junction grading coefficient. (Default = .33) Alternate names are MJ and MC.

MJE = x
B-E junction grading coefficient. (Default = .33) Alternate name is ME.

MJS = x
Substrate junction grading coefficient. (Default = 0) Alternate names are MS and MSUB.

VJC = x
B-C built in potential. (Default = .75) Alternate name is PC.

VJE = x
B-E built in potential. (Default = .75) Alternate name is PE.

VJS = x
Substrate junction built in potential. (Default = .75) Alternate name is PS.

XCJC = x
Fraction of B-C capacitance connected to internal base node. (Default = 1)

Parasitic capacitance

CBCP = x
External B-C constant parasitic capacitance. (Default = 0)

CBEP = x
External B-E constant parasitic capacitance. (Default = 0)

CBSP = x
External B-S constant parasitic capacitance for lateral transistors. (Default = 0)

CCSP = x
External B-C constant parasitic capacitance for vertical transistors. (Default = 0)

Transit time

ITF = x
High current dependence of TF. (Default = 0)

PTF = x
Excess phase at freq=1.0/(TF*2PI) Hz. (Default = 0)

TF = x
Ideal forward transit time. (Default = 0)

TR = x
Ideal reverse transit time. (Default = 0)

VTF = x
Voltage giving VBC dependence of TF. (Default = Infinite)

XTF = x
Coefficient for bias dependence of TF. (Default = 0)

Temperature effects

XTB = x
Forward and reverse beta temperature exponent. (Default = 0)

XTI = x
Temperature exponent for effect on IS. (Default = 3)

EG = x
Energy gap for IS temperature dependency. (Default = 1.11)

TNOM = x
Parameter measurement temperature, Celsius. (Default = 27)

3.17.6  Probes

VBEInt
Base-emitter internal voltage.

VBCInt
Base-collector internal voltage.

VBXInt
External base to internal base voltage.

VCSInt
Collector-substrate internal voltage.

VBS
Base-substrate voltage.

VBE
Base-emitter voltage.

VBC
Base-collector voltage.

VCS
Collector-substrate voltage.

VCB
Collector-base voltage.

VCE
Collector-emitter voltage.

VES
Emitter-substrate voltage.

VEB
Emitter-base voltage.

VEC
Emitter-collector voltage.

VB
Base-ground voltage.

VC
Collector-ground voltage.

VE
Emitter-ground voltage.

VS
Substrate-ground voltage.

VBI
Internal Base-ground voltage.

VCI
Internal Collector-ground voltage.

VEI
Internal Emitter-ground voltage.

ICE
Collector-emitter current.

ICEOffset
Offset part of ICE.

GO
Output (collector-emitter) conductance.

GM
Transconductance.

IPI
Base-emitter current.

IPIOffset
Offset part of IPI.

GPI
Base-emitter conductance.

IMU
Base-collector current.

IMUOffset
Offset part of IMU.

GMU
Base-collector conductance.

IB
Base current.

GX
Conductance of base spreading resistance.

RX
Base spreading resistance.

IC
Collector current.

IE
Emitter current.

QBX
External Base-collector charge.

CQBX
External Base-collector capacitance.

CBX
External Base-collector capacitance (CQBX).

QBC
Internal Base-collector charge.

CQBC
Internal Base-collector capacitance.

CBC
Internal Base-collector capacitance (CQBC).

CMU
Internal Base-collector capacitance (CQBC).

QCS
Collector-substrate charge.

CQCS
Collector-substrate capacitance.

CCS
Collector-substrate capacitance (CQCS).

QBE
Base-emitter charge.

CQBE
Base-emitter capacitance.

CBE
Base-emitter capacitance. (CQBE).

CPI
Base-emitter capacitance. (CQBE).

P
Power.

PD
Power dissipated. The power dissipated as heat. It is always positive and does not include power sourced. It should be the same as P because transistors cannot generate energy.

PS
Power sourced. The power sourced by the part. It is always positive and does not consider its own dissipation. It should be 0 because transistors cannot generate energy.
All parameters of the internal elements (Ice, Ipi, Imu, Rc, Re, Yb, Cbx, Cbc, Ccs, Cbe, Cbcp, Cbep, Cbsp, Ccsp) are available. To access them, concatenate the labels for the internal element with this device, separated by a dot. Cbe.Q6 is the base to emitter capacitance of Q6.

In this release, there are no probes available in AC analysis except for the internal elements.

3.18  R: Resistor

3.18.1  Syntax

Rxxxxxxx n+ n-- value
Rxxxxxxx n+ n-- expression
Rxxxxxxx n+ n-- model {L=length} {W=width} {TEMP=temperature}
.RESistor label n+ n-- expression

3.18.2  Purpose

Resistor, or general current controlled dissipative element.

3.18.3  Comments

N+ and n-- are the positive and negative element nodes, respectively. Value is the resistance in Ohms.

The resistor (type R) differs from the admittance (type Y) in that the resistor is a current controlled element, and the conductance is a voltage controlled element, in addition to the obvious use of conductance (1/R) instead of resistance.

You may specify the value in one of three forms:
  1. A simple value. This is the resistance in Ohms.

  2. An expression, as described in the behavioral modeling chapter. The expression can specify the voltage as a function of current, or the resistance as a function of time.

  3. A model, which calculates the resistance as a function of length and width, referencing a .model statement of type R. This is compatible with the Spice-3 ``semiconductor resistor''.

3.18.4  Model statement

A model statement may be used,, with model type R or Res. The parameters are:
RSH = x
Sheet resistance. (Ohms / square). (Required)

CJSW = x
Junction sidewall capacitance. (Farads / meter). (Default = 0.)

DEFW = x
Default width. (meters). (Default = 1e-6)

NARROW = x
Narrowing due to side etching. (meters). (Default = 0.)

TC1 = x
First order temperature coefficient. (Farads / degree C). (Default = 0.)

TC2 = x
Second order temperature coefficient. (Farads / degree C squared). (Default = 0.)

TNOM = x
Parameter measurement temperature. (degrees C.). (Default = 27.)
Resistance is computed by the formula:
resistance = RSH * (L - NARROW) / (W - NARROW)
After the nominal value is calculated, it is adjusted for temperature by the formula:
value *= (1 + TC1 * (T-T0) + TC2 * (T-T0)^2)

3.19  S: Voltage Controlled Switch

3.19.1  Syntax

Sxxxxxxx n+ n-- nc+ nc-- mname {ic}
.VSWitch label n+ n-- nc+ nc-- mname {ic}

3.19.2  Purpose

Voltage controlled switch.

3.19.3  Comments

N+ and n-- are the positive and negative element nodes, respectively. Nc+ and nc-- are the controlling nodes. Mname is the model name. A switch is a resistor between n+ and n--. The value of the resistor is determined by the state of the switch.

The resistance between n+ and n-- will be RON when the controlling voltage (between nc+ and nc--) is above VT + VH. The resistance will be ROFF when the controlling voltage is below VT - VH. When the controlling voltage is between VT - VH and VT + VH, the resistance will retain its prior value.

You may specify ON or OFF to indicate the initial state of the switch when the controlling voltage is in the hysteresis region.

RON and ROFF must have finite positive values.

3.19.4  Model Parameters

VT = x
Threshold voltage. (Default = 0.)

VH = x
Hysteresis voltage. (Default = 0.)

RON = x
On resistance. (Default = 1.)

ROFF = x
Off resistance. (Default = 1e12)

3.20  T: Transmission Line

3.20.1  Syntax

Txxxxxxx n1+ n1-- n2+ n2-- {args}
.TLIne xxxxxxx n1+ n1-- n2+ n2-- {args}

3.20.2  Purpose

Lossless transmission line.

3.20.3  Comments

N1+ and n1-- are the nodes at one end. N2+ and n2-- are the nodes at the other end.

The parameters TD, Freq, and NL determine the length of the line. Either TD or Freq and NL must be specified. If only Freq is specified, NL is assumed to be .25. The other will be calculated based on the one you specify. If you specify too much, Freq and NL dominate, and a warning is issued.

3.20.4  Element Parameters

Z0 = x
Characteristic impedance. (Default = 50.)

TD = x
Time delay.

Freq = x
Frequency for NL.

NL = x
Number of wavelengths at Freq.

3.21  U: Logic Device

3.21.1  Syntax

Uxxxxxxx out gnd vdd enable in1 in2 ... family gatetype

3.21.2  Purpose

Logic element for mixed or logic mode simulation.

3.21.3  Comments

A sample 2 input nand gate might be: U102 5 0 34 34 2 3 cmos nand. The input pins are connected to nodes 2 and 3. The output is at node 5. Node 34 is the power supply.

The logic element behaves differently depending on the options analog, mixed, or digital. You set one of these with the options command. Analog mode substitutes a subcircuit for the gate for full analog simulation. Digital mode simulates the gate as a digital device as in an event driven gate level logic simulator. Mixed mode applies heuristics to decide whether to use analog or digital for each gate.

In analog mode the logic (U) device is almost the same as a subcircuit (X). The subcircuit is user defined for each gate type used. A .subckt defines the analog equivalent of a logic element. The name of the subcircuit is made by concatenating the family, gatetype, and the number of inputs. For example, if the family is cmos and the gatetype is nand and it has two inputs, the name of the subcircuit is cmosnand2. So, the gate in the first paragraph becomes equivalent to: X 5 0 34 34 2 3 cmosnand2. You then need to define the subcircuit using the standard .subckt notation. You can probe the internal elements the same as an ordinary subcircuit.

The digital mode uses simple boolean expressions to compute the output, just like a gate level logic simulator. In this case the output is computed by L(5) = not(L(2) and L(3)) where L(2) is the logic state at node 2. The simulator exploits latency so it will only compute the output if one of the inputs changes. The output actually changes after a delay, specified in the .model statement. There are no conversions between digital and analog where gates connect together. There will be an automatic conversion from analog to digital for any input that is driven by an analog device. There will be an automatic conversion from digital to analog for any output that drives an analog device. These conversions will only be done if they are needed. You can probe the analog value at any node. The probe will automatically request the conversion if it needs it. There is no internal subcircuit so it is an error to probe the internal elements.

The mixed mode is a combination of analog and digital modes on a gate by gate basis. Some gates will be analog. Some will be digital. This will change as the simulation runs based on the quality of the signals. You need to specify a .subckt as you do for the analog mode, but the simulator may not use it. You can usually not probe the elements inside the subcircuit because they come and go.

3.21.4  Element Parameters

Family refers to the logic family .model statement.

Gatetype is the type of logic gate:
AND


NAND


OR


NOR


XOR


INV

3.21.5  Model Parameters

Parameters used in digital mode

DElay = x
Propagation delay. (Seconds) (Default = 1e-9) The propagation delay of a simple gate when simulated in logic mode.

Parameters used in conversion both ways

VMAx = x
Nominal logic 1. (Volts) (Default = 5.) The nominal value for a logic 1.

VMIn = x
Nominal logic 0. (Volts) (Default = 0.) The nominal value for a logic 0.

Unknown = x
Nominal logic unknown. (Volts) (Default = (vmax+vmin)/2) The output voltage for a logic unknown. In a real circuit, this voltage is unknown, but a simulator needs something, so here it is.

Digital to Analog conversion

RIse = x
Rise time. (Seconds) (Default = delay / 2) The nominal rise time of a logic signal. This will be the rise time when a logic signal is converted to analog.

FAll = x
Fall time. (Seconds) (Default = delay / 2) The nominal fall time of a logic signal. This will be the fall time when a logic signal is converted to analog.

RS = x
Series resistance, strong. (Ohms) (Default = 100.) The resistance in series with the output when a logic gate drives analog circuitry.

RW = x
Series resistance, weak. (Ohms) (Default = 1e9) The output resistance in a high impedance state.

Analog to Digital conversion

THH = x
Threshold high. (Unitless) (Default = .75) The threshold for the input to cross from transition to high expressed as a fraction of the difference between high and low values. (Low = 0. High = 1.)

THL = x
Threshold low. (Unitless) (Default = .25) The threshold for the input to cross from transition to low expressed as a fraction of the difference between high and low values. (Low = 0. High = 1.)

Mode decision parameters

MR = x
Margin rising. (Unitless) (Default = 5) How much worse than nominal the analog input rise time can be and still be accepted as clean enough for logic simulation.

MF = x
Margin falling. (Unitless) (Default = 5) How much worse than nominal the analog input fall time can be and still be accepted as clean enough for logic simulation.

OVer = x
Overshoot limit. (Unitless) (Default = .1) How much overshoot can a signal have and still be accepted as clean enough for logic simulation, expressed as a fraction of the difference between high and low values. (Low = 0. High = 1.)

3.21.6  Probes

V
Output voltage.
In this release, there are no probes available in AC analysis except for the internal elements. Internal elements in the analog model are available, but they come and go so they may be unreliable. More parameters will be added.

You can probe the logic value at any node. See the print command for details.

3.22  V: Independent Voltage Source

3.22.1  Syntax

Vxxxxxxx n+ n-- value
Vxxxxxxx n+ n-- expression
.VSOurce label n+ n-- expression

3.22.2  Purpose

Independent voltage source.

3.22.3  Comments

N+ and n-- are the positive and negative element nodes, respectively. Value is the voltage in Volts.

All of the SPICE time dependent functions (pulse, sin, exp, pwl, and sffm are supported. An additional function generator emulates a laboratory type function generator, for a more convenient signal input to the circuit.

3.23  W: Current Controlled Switch

3.23.1  Syntax

Wxxxxxxx n+ n-- ce mname {ic}
.ISWitch label n+ n-- ce mname {ic}

3.23.2  Purpose

Current controlled switch.

3.23.3  Comments

N+ and n-- are the positive and negative element nodes, respectively. Ce is the name of an element through which the controlling current flows. Mname is the model name. A switch is a resistor between n+ and n--. The value of the resistor is determined by the state of the switch.

The resistance between n+ and n-- will be RON when the controlling current (through ce) is above IT + IH. The resistance will be ROFF when the controlling current is below IT - IH. When the controlling current is between IT - IH and IT + IH, the resistance will retain its prior value.

You may specify ON or OFF to indicate the initial state of the switch when the controlling current is in the hysteresis region.

RON and ROFF must have finite positive values.

The controlling element can be any simple two terminal element. Unlike SPICE, it does not need to be a voltage source.

3.23.4  Model Parameters

IT = x
Threshold current. (Default = 0.)

IH = x
Hysteresis current. (Default = 0.)

RON = x
On resistance. (Default = 1.)

ROFF = x
Off resistance. (Default = 1e12)

3.24  X: Subcircuit Call

3.24.1  Syntax

Xxxxxxxx n1 {n2 n3 ...} subname

3.24.2  Purpose

Subcircuit call

3.24.3  Comments

Subcircuits are used by specifying pseudo-elements beginning with X, followed by the connection nodes.

3.24.4  Probes

Vx
Port (terminal node) voltage. x is which port to probe. 1 is the first node in the "X" statement, 2 is the second, and so on.

P
Power. The sum of the power probes for all the internal elements.

PD
Power dissipated. The total power dissipated as heat.

PS
Power sourced. The total power generated.
In this release, there are no probes available in AC analysis except for the internal elements. More parameters will be added. Internal elements can be probed by concatenating the internal part label with the subcircuit label. R5.X7 is R5 inside X7.

3.25  Y: Admittance

3.25.1  Syntax

Yxxxxxxx n+ n-- value
Yxxxxxxx n+ n-- expression
.ADMittance label n+ n-- expression

3.25.2  Purpose

Admittance, or general voltage controlled dissipative element.

3.25.3  Comments

N+ and n-- are the positive and negative element nodes, respectively. Value is the admittance in Mhos.

The resistor (type R) differs from the admittance (type Y) in that the resistor is a current controlled element, and the conductance is a voltage controlled element, in addition to the obvious use of conductance (1/R) instead of resistance.
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